Implementation of Multi-Bit flip-flop for Power Reduction in CMOS Technologies

Nowadays Power has become a major concern in low power VLSI design. Achieving low power consumption is a tedious one in IC fabrication industries. In modern integrated circuits, clocking is the most dominating power consuming element. Hence this paper describes a method for reducing the power consumption by replacing some flip-flops with fewer multi-bit flip-flops. We perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wire length is also considered. This algorithm can reduce clock power and the running time is very short.